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? semiconductor components industries, llc, 2012 july, 2012 ? rev. 0 1 publication order number: nct80/d nct80 hardware monitor with i 2 c serial interface the nct80 is a two ? wire serially programmable hardware monitor. it can monitor its on chip temperature via its local sensor, 7 analog inputs and measure the speed of two fans. each of the measured values are compared with programmable limits and if any channel is outside the programmed limit an interrupt is generated via the int output pin. it also has a chassis intrusion detection input pin which is latched on an intrusion event. communication with the nct80 is accomplished via the i 2 c interface which is compatible with industry standard protocols. through this interface the nct80s internal registers may be accessed. these registers allow the user to read the current temperature, fan speed and voltages, change the configuration settings and adjust each channels limits. the nct80 is available in a 24 ? lead tssop package and operates over a wide supply range of 2.8 to 5.75 v. this makes the nct80 ideal for a wide variety of applications ranging from computers to servers and test equipment. features ? on ? chiptemperature sensor ? 2 fan speed monitoring inputs ? 7 analog inputs for voltage monitoring ? chassis intrusion detection ? overtemperature output ? limit comparison of monitored channels ? 3 address selection pins ? power saving shutdown mode ? i 2 c compliant interface ? these devices are pb ? free, halogen free/bfr free and are rohs compliant tssop ? 24 db suffix case 948h (top view) pin connections ordering information http://onsemi.com device package shipping ? NCT80DBR2G tssop ? 24 (pb ? free) tape & reel xxxxx xxxxg alyw xxxx = specific device code a = assembly location l = wafer lot y = year w = work week g = pb ? free package ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. int_in sda scl tach1 tach2 bti ci gnd v dd int gpo rst_in / ntest_in rst_out / therm a2 a1 a0/ntest_out ain0 ain1 ain2 ain3 ain4 ain5 ain6 agnd 1
nct80 http://onsemi.com 2 a ? to ? d converter on ? chip temperature sensor analog mux i2c interface 3 2 4 5 7 gnd sda scl a1 10 ain0 ain1 a0 6 9 ain2 ain3 8 11 12 1 14 a2 ci 17 19 22 15 20 13 16 21 18 23 24 ain6 ain5 ain4 fan counter limit and config limit comparitor data status register interrupt control ci agnd nct80 tach1 tach2 figure 1. functional block diagram of nct80 bti int_in int rst_out / therm ntest_in / rst_in gpo registers registers speed v dd table 1. pin function description pin no. pin name description 1 int_in active low digital input. this signal is propagated to the int output pin of the nct80. 2 sda i 2 c serial bi ? directional data input/output. open ? drain pin; needs a pull ? up resistor. 3 scl serial clock input. open ? drain pin; needs a pull ? up resistor. 4 tach1 digital input. fan tachometer input to measure speed of fan. 5 tach2 digital input. fan tachometer input to measure speed of fan. 6 bti digital input. board temperature interrupt driven by o.s. outputs of additional temperature sensors such as the nct75. 7 ci (chassis intrusion) digital i/o. an active high input from an external latch which captures a chassis intrusion event. this line can go high without any clamping action, regardless of the powered state of the nct80 8 gnd power supply ground. 9 v dd positive supply voltage. bypass to ground with a 0.1 f bypass capacitor. 10 int digital output. open drain interrupt request pin. 11 gpo digital output. an active low open drain output intended to drive an external p ? channel power mosfet in order to offer software power control. 12 ntest_in /rst_in dual function pin. active low input that enables nand tree test functionality. once enabled the part is reset to its power on default. 13 rst_out /therm dual function pin. rst_out: active low reset output pin. therm : overtemperature shutdown output pin. 14 agnd analog ground. 15 ain6 analog input. 0 v to 2.56 v. 16 ain5 analog input. 0 v to 2.56 v. 17 ain4 analog input. 0 v to 2.56 v. 18 ain3 analog input. 0 v to 2.56 v. 19 ain2 analog input. 0 v to 2.56 v. 20 ain1 analog input. 0 v to 2.56 v. 21 ain0 analog input. 0 v to 2.56 v. 22 a0/ntest_out dual function pin. functions as an i 2 c address selection bit. this is the lsb of the address. pin also functions as an output when performing a nand test. 23 a1 functions as an i 2 c address selection bit. 24 a2 functions as an i 2 c address selection bit.
nct80 http://onsemi.com 3 table 2. absolute maximum ratings rating symbol value unit supply voltage (v dd ) v dd ? 0.3 to +6.5 v voltage on any input or output pin ? 0.3 to v dd + 0.3 v input current at any pin i in 5 ma maximum junction temperature t j(max) 150.7 c storage temperature range t stg ? 65 to 160 c esd capability, human body model (note 2) esd hbm 2500 v esd capability, machine model (note 2) esd cdm 1000 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. refer to electrical characteristics and application information for safe operating area. 2. this device series incorporates esd protection and is tested by the following methods: esd human body model tested per aec ? q100 ? 002 (eia/jesd22 ? a114) esd machine model tested per aec ? q100 ? 003 (eia/jesd22 ? a115) table 3. operating ranges rating symbol min max unit operating supply voltage v dd 2.8 5.75 v operating ambient temperature range t a ? 40 125 c 3. refer to electrical characteristics and application information for safe operating area. table 4. electrical characteristics (t a = t min to t max , v dd = 2.8 v to 5.75 v. all specifications for ? 40 c to +125 c, unless otherwise noted.) parameter test conditions min typ max unit power supply characteristics supply voltage 2.8 5.75 v supply current interface inactive 0.580 ma shutdown current shutdown mode enabled 200 a temperature to digital converter characteristics local sensor accuracy v dd = 2.8 v to 5.75 v t a = 0 c to +100 c 2 c t a = ? 40 c to +125 c 3 c resolution 0.0625 c analog ? to ? digital converter characteristics adc resolution (bits) 10 bits resolution (10 bits with full ? scale at 2.56 v) 2.5 mv total unadjusted error (tue) 1 % differential nonlinearity (dnl) 1 lsb round robin cycle time 662 728 810 ms multiplexer/adc input characteristics on resistance 11.5 13 k input current (on channel leakage current) 0.005 a off channel leakage current 0.005 a fan rpm ? to ? digital converter fan rpm error t a = ? 40 c to +125 c 10 % full scale count 255 (max) tach1 & tach2 nominal input rpm divisor = 1, fan count = 153 8800 rpm
nct80 http://onsemi.com 4 table 4. electrical characteristics (t a = t min to t max , v dd = 2.8 v to 5.75 v. all specifications for ? 40 c to +125 c, unless otherwise noted.) parameter unit max typ min test conditions fan rpm ? to ? digital converter tach1 & tach2 nominal input rpm divisor = 2, fan count = 153 4400 rpm divisor = 3, fan count = 153 2200 rpm divisor = 4, fan count = 153 1100 rpm internal clock frequency 20.2 22.5 24.8 khz digital outputs (a0/ ntest_out , int ) output high voltage, logical ?1? i out = +5.0 ma, v dd = 2.8 v ? 5.75 v 2.4 v output low voltage, logical ?0? i out = ? 5.0 ma, v dd = 2.8 v ? 5.75 v 0.4 v open drain outputs (gpo , rst_out /os , ci, sda) output low voltage, logical ?0? i out = +5.0 ma, v dd = 3.6 v 0.4 v high level output current v out = v dd 0.1 1 a rst_out /os , ci pulse width 10 22.5 ms digital inputs (except for bti ) input high voltage, logical ?1? 0.7 x v dd v input low voltage, logical ?0? 0.3 x v dd v all digital inputs (except for bti ) input current (logical ?1?) v in = v dd ? 1 ? 0.005 a input current (logical ?0?) v in = 0 v 0.005 1 a input capacitance 20 pf bti digital input input current (logical ?1?) v in = v dd ? 10 a input current (logical ?0?) v in = 0 v 2000 a input capacitance 20 pf table 5. i 2 c timing parameter (note 4) symbol min typ max unit clock frequency f sclk 10 400 khz clock period t 1 2.5 100 s data setup time (note 5) t 2 100 ns data out stable t 3 0 0.9 s start hold time (note 6) t 4 100 ns stop setup time t 5 100 ns scl high time t 6 0.6 s scl low time t 7 1.3 s start setup time t 8 0.6 s scl, sda rise time t 9 300 ns scl, sda fall time t 10 300 ns bus free time t 11 1.3 s glitch immunity t 12 0 50 ns timeout t timeout 25 35 ms 4. guaranteed by design, but not production tested. 5. time for 10% or 90% of sda to 10% of scl. 6. time from 10% of sda to 90% of scl.
nct80 http://onsemi.com 5 typical characteristics figure 2. supply current vs. v dd figure 3. supply current vs. v dd (voltage conversion) v dd (v) 5.8 5.3 4.8 4.3 3.8 3.3 2.8 0 100 200 300 400 500 600 figure 4. supply current vs. v dd (temperature conversion) figure 5. shutdown current vs. v dd figure 6. tue vs. code figure 7. local temp error vs. v dd i dd ( a) 5.8 5.3 4.8 4.3 3.8 3.3 2.8 0 100 200 300 400 500 600 i dd ( a) v dd (v) v dd (v) 5.8 5.3 4.8 4.3 3.8 3.3 2.8 0 100 200 300 400 500 600 i dd ( a) 5.8 5.3 4.8 4.3 3.8 3.3 2.8 0 100 200 300 400 500 600 i dd ( a) v dd (v) 5.75 5.0 4.5 4.125 3.6 3.0 2.8 ? 1.0 ? 0.6 ? 0.2 0 0.2 0.6 1.0 i dd (a) v dd (v) 3.3 ? 0.4 ? 0.8 0.4 0.8 22 23 24 25 26 28 29 15 16 17 18 19 20 8 9 10 11 12 13 14 1 2 3 4 5 6 7 21
nct80 http://onsemi.com 6 scl sda stop start stop start figure 8. serial interface timing t 5 t 11 t 4 t 3 t 7 t 9 t 10 t 2 t 6 t 4 t 8 theory of operation the nct80 contains an on chip local temperature sensor, an 8 channel multiplexer, a 10 bit sigma ? delta analog to digital converter and different internal registers in a single package. it has the capability to monitor 7 analog inputs ain0 ? ain6. the ef fective use of these analog inputs can be accomplished by connecting them to monitor different power supplies level present in any communication system. it also has two fan speed measurement inputs that can be configured either as fan failure signal or the tachometer signal. the fan inputs are digital signals with transition levels according to the fan tach pulse inputs in the electrical characteristics table. the signal conditioning circuitry is present on the chip to accommodate slow rise and fall times. the nominal fan speeds are programmable from 1100 to 8800 rpm (based on count of 153). full scale fan counts are 255 (8bit counter) which represents a very slow or stopped fan. the communication interface with the device is accomplished by an i 2 c interface that is compatible to both standard mode and fast mode operations. the standard and fast modes correspond to 100 khz and 400 khz. nct80 also has a three address selection pins a0 ? a2 that facilitate the use of eight devices on a single bus. internal registers in this section the overview of important internal registers is presented. nct80 contains 41 internal registers the details of whom can be seen in the register map section. configuration register: this register can be accessed for control and configuration. interrupt status registers: there are two registers that provide the status of each interrupt alarm. continuous reading of the status register can make the bits in the register toggle intermittently and momentarily clears the int pin also. interrupt mask registers: these registers can be accessed for masking of individual interrupt sources, as well as separate masking for both hardware interrupt outputs. fan divisor output pin configuration: this register can be accessed to configure fan reading modes and also the os and rst_out pin configuration. bits 0 to 5 of this register contain the divisor bits for the tach1 and tach2 inputs. bits 6 and 7 control the function of the rst_out /os output. os configuration/temperature resolution register: this register can be accessed to configure the os output pin and the temperature sensor resolution. the resolution can be configured either 9 bit or 12 bit. bit 3 enables 12 ? bit temperature conversions. in 12 ? bit mode, bits 4 to 7 represent the four lsbs of the temperature measurement. in 9 ? bit mode, bit 4 represents the lsb of the temperature measurement. conversion rate register: this register can be accessed to control the conversion rate of the adc. channel add/remove register: this register can be accessed by the user to manually add or remove measurement channels from the adc. ram registers: the results for monitoring fan counts, temperature, voltages etc are all contained in it. it consists of 31 bytes with the first 10 bytes are the results and the next 20 bytes are the interrupt alarm limit registers. limit values for analog measurements are stored in the appropriate limit registers. in the case of voltage measurements, high and low limits can be stored so that an interrupt request will be generated if the measured value goes above or below acceptable values. in the case of temperature, a hot temperature (high limit), and a hot t emperature hysteresis (low limit) can be programmed. the hysteresis value is usually a few degrees lower than the high limit. these limits allow the system to be shut down when the hot limit is exceeded and restarted automatically when the temperature has dropped below the hysteresis limit. the last byte is the upper locations for manufacturer id. application details power ? on_reset when nct80 is turned on by applying power to v dd pin it undergoes to a reset mode where most of the internal registers are reset. the interrupt and ram registers do not reset on power on and their values are determined immediately after the reset process. the configuration register bit 7 has the same function as the power on reset. this bit can be set to 1 to initiate the reset process which clears automatically afterwards. initiating inputs monitoring the monitoring cycle of the nct80 begins when a one is written to the start bit (bit 0) and a zero to the int_clear bit (bit 3) of the configuration register. when the nct80 monitoring sequence is started, it cycles sequentially
nct80 http://onsemi.com 7 through the measurement of the 7 analog inputs. each input is multiplexed separately into the nct80?s 10 bit adc and stored in the appropriate value register. the on ? chip temperature sensor is monitored through a 12 bit sigma delta adc giving the temperature a resolution of 0.0625 c. at the same time the fan speed inputs are independently monitored. once each conversion is completed the data is compared with programmed limits stored in the limit registers of ram. it can then be read back over the serial bus. the sequence of items that are monitored except for the temperature reading corresponds to locations in the ram registers as follows: 1. temperature 2. ain0 3. ain1 4. ain2 5. ain3 6. ain4 7. ain5 8. ain6 9. tach 1 10. tach 2 reading results the conversion results are stored in the value registers at addresses from 20h to 29h. these conversion results can be read at any time and correspond to the result of the last conversion. a typical sequence of events after nct80 power ? on is as follows: 1. set alarm limits 2. set interrupt masks 3. start the nct80 monitoring process analog inputs nct80 has a 10 ? bit adc which has an lsb value of 2.5 mv. the input has a full scale input range of 0 to 2.56 v. the analog inputs are often connected to power supplies whose values can be 2.5, 3.3, 5 or 12 v. this poses a requirement to attenuate the voltage inputs within the acceptable input range of the adc. voltage divider can be used to attenuate the analog input voltages with in the desired range. for any applications a voltage divider with an output signal of 1.9 v to the analog inputs will be an appropriate selection. this selection will give a tolerance for upward excursion in the power supply of 25%. 10 ? bit adc & multiplexer 0 ? 2.56 vin ain0 ain1 ain2 ain3 ain4 ain5 ain6 temperature supply figure 9. resistor divider to attenuate the power supply voltage within required range r 1 r 2 the selection of resistors value can be simplified by first selecting the value of r 2 . the value of r 2 should be high enough to protect both inputs under overdrive conditions and must be low enough to avoid leakage current errors. a typical value for r 2 with in 10 k ? 100 k range will serve this purpose. the value of r1 then can be selected to provide 1.9 v at the ainx pins as follows: r 1 supply 1.9 1.9 r 2 it is necessary to limit input currents to avoid the absolute maximum rating value. extra external resistors must be used to achieve this at any pin. temperature measurement temperature data can be read from the temperature reading register at 27h. temperature limits can be read from and written to the hot temperature, hot temperature hysteresis, os temperature, and os temperature hysteresis limit registers. these registers have addresses from 38h to 3bh respectively. the temperature data limit is represented by 8 bit, 9 bit and 12 bit two?s complement word with an lsb equal to 1 c. table 6. 8 bit temperature data representation temperature binary output hex output +125 c 0111 1101 7dh +25 c 0001 1001 19h +1 c 0000 0001 01h +0 c 0000 0000 00h ? 1 c 1111 1111 ffh ? 25 c 1110 0111 e7h ? 55 c 1100 1001 c9h table 7. 9 bit temperature data representation temperature binary output hex output +125 c 0 1111 1010 0 fah +25 c 0 0011 0010 0 32h +1.5 c 0 0000 0011 0 03h +0 c 0 0000 0000 0 00h ? 0.5 c 1 1111 1111 1 ffh ? 25 c 1 1100 1110 1 ceh ? 55 c 1 1001 0010 1 92h
nct80 http://onsemi.com 8 table 8. 12 bit temperature data representation temperature binary output hex output +125 c 0111 1101 0000 7 d0h +25 c 0001 1001 0000 1 90h +1 c 0000 0001 0000 0 10h +0.0625 c 0000 0000 0001 0 01h +0 c 0000 0000 0000 0 00h ? 0.0625 c 1111 1111 1111 f ffh ? 1.0 c 1111 1111 0000 f f0h ? 25 c 1110 0111 0000 e 70h ? 55 c 1100 1001 0000 c 90h when using a single ? byte read, the eight msbs of the temperature reading can be found in the value ram register at 27h. the remainder of the temperature reading can be found in the os_config_temp_resolution register at address 06h, bits 4 to 7. in 9 ? bit format, bit 7 is the only valid bit. in addition, all nine or 12 bits can be read using a double ? byte read at register address 27h. temperature interrupts there are four value ram register limits for the temperature reading that affect the int and os outputs of the nct80. these are the hot_temp_high_limit (hthl), hot_temp_hysteresis_limit (htht_hyst), os_temp_high_limit (tos) and os_temp_ hysteresis_limit (t os _hyst) having address from 38h ? 3bh. there are three interrupt modes of operation: default interrupt, one ? time interrupt, and comparator. the os output of the nct80 can be programmed for one ? time interrupt mode and comparator mode. int can be programmed for default interrupt mode and one ? time interrupt mode. these modes are explained in the following subsections. default interrupt mode in default interrupt mode, exceeding hthl causes an interrupt that remains active indefinitely until reset by reading interrupt status register 1 at address 01h or cleared by the int_clear bit in the configuration register at address 00 h, bit 3. when an interrupt event has occurred by exceeding hthl, and is then reset, another interrupt occurs again when the next temperature conversion has completed. the interrupts continue to occur in this manner until the temperature falls below hthl_hyst, at which time the interrupt output automatically clears. one ? time interrupt mode in one ? time interrupt mode, exceeding hthl causes an interrupt that remains active indefinitely until reset by reading interrupt status register 1 or cleared by the int_clear bit in the configuration register. when an interrupt event has occurred by exceeding hthl, and is then reset, an interrupt does not occur again until the temperature falls below hthl_hyst. comparator mode in comparator mode, exceeding t os causes the os output to go low (default) and remain low until the temperature falls below t os _hyst. when the temperature falls below t os _hyst, os goes high. chassis intrusion a chassis intrusion input (pin 7) is provided to detect unauthorised tampering with the equipment. reset a reset input (pin 12) and reset output (pin 13) is also provided. pulling the input pin low will reset all the nct80 internal registers to their default values. this pin must be pulled high in order for the user to be able to configure the device. the reset output is at least 10 ms. adc converter the analog inputs (ain0 ? ain6) are multiplexed into the on ? chip successive approximation, analog ? digital converter. this has a resolution of 10 bits. the basic input range is zero to 2.56 v. when the adc is running, it samples and converts an input every 728 ms, except for the internal temperature. this is converted using a sigma delta adc. fan monitoring cycle time when a monitoring cycle is started, monitoring of the fan speed inputs begins at the same time as monitoring of the analog inputs. however, the two monitoring cycles are not synchronized in any way. the monitoring cycle time for the fan inputs is dependent on fan speed and is much slower than for the analog inputs. the monitoring cycle time depends on the fan speed and number of tach output pulses per revolution. two complete periods of the fan tach output (three rising edges) are required for each fan measurement. therefore, if the start of a fan measurement just misses a rising edge, the measurement can take almost three tach periods. in order to read a valid result from the fan value registers, the total monitoring time allowed after starting the monitoring cycle should, therefore, be three tach periods of tach1 plus three tach periods of tach2 at the lowest normal fan speed. fan inputs pins 4 and 5 are fan speed inputs. signal conditioning in the nct80 accommodates the slow rise and fall times typical of fan tachometer outputs. the maximum input signal range is 0 to vcc. in the event that these inputs are supplied from fan outputs that exceed 0 v to 6.5 v, either resistive attenuation of the fan signal or diode clamping must be included to keep inputs within an acceptable range. figure 10 to figure 13 show circuits for most common fan tach outputs. if the fan tach output has a resistive pull ? up to vcc it can be directly connected to the fan input, as shown in figure 10 .
nct80 http://onsemi.com 9 figure 10. fan with tach. pull ? up to +vcc if the fan output has a resistive pull ? up to 12 v (or other voltage greater than 6.5 v), the fan output can be clamped with a zener diode, as shown in figure 11. the zener voltage should be chosen so it is greater than vih but less than 6.5 v, allowing for the voltage tolerance of the zener. a value of between 3 v and 5 v is suitable. figure 11. fan with tach. pull ? up to voltage >6.5 v if the fan has a strong pull ? up (less than 1 k ) to 12 v, or a totem ? pole output, then a series resistor can be added to limit the zener current, as shown in figure 1 2. alternatively, a resistive attenuator may be used, as shown in figure 13. r1 and r2 should be chosen such that: 2v v pull ? up r 2 r pull ? up r 1 r 2 5v the fan inputs have an input resistance of nominally 160 k to ground, so this should be taken into account when calculating resistor values. with a pull ? up voltage of 12 v and pull ? up resistor less than 1 k , suitable values for r1 and r2 would be 100 k figure 12. fan with strong tach. pull ? up to >vcc or totem ? pole output, clamped with zener and resistor
nct80 http://onsemi.com 10 figure 13. fan with strong tach. pull ? up to >vcc or totem ? pole output, attenuated with r1/r2 fan speed measurement the fan counter does not count the fan tach output pulses directly, because the fan speed may be less than 1000 rpm and it would take several seconds to accumulate a reasonably large and accurate count. instead, the period of the fan revolution is measured by gating an on ? chip 22.5 khz oscillator into the input of an 8 ? bit counter for two periods of the fan tach output, as shown in figure 14; the accumulated count is actually proportional to the fan tach period and inversely proportional to the fan speed. 22.5 khz clock configuration reg. 1 bit 0 fan0 input fan0 measurement period fan1 measurement period start of monitoring cycle fan1 input 1 2 34 123 4 figure 14. fan speed measurement the measurement begins on the rising edge of a fan tach pulse, and ends on the next ? but ? one rising edge. the fans are monitored sequentially, so if only one fan is monitored the monitoring time is the time taken after the start bit for it to produce two complete tach cycles or for the counter to reach full scale, whichever occurs sooner. if more than one fan is monitored, the monitoring time depends on the speed of the fans and the timing relationship of their tach pulses. this is illustrated in figure 14. once the fan speeds have been measured, they will be stored in the fan speed value registers and the most recent value can be read at any time. the measurements will be updated as long as the monitoring cycle continues. to accommodate fans of different speed and/or different numbers of output pulses per revolution, a prescaler (divisor) of 1, 2, 4, or 8 may be added before the counter. the default value is 2, which gives a count of 153 for a fan running at 4400 rpm producing two output pulses per revolution. the count (stored in the tach registers) is calculated by the equation: count (22.5 10 3 60) (rpm divisor) 22.5x10 3 = oscillator frequency divisor = number of poles in the fan fan limit values fans in general will not over speed if run from the correct voltage, so the failure condition of interest is under speed due to electrical or mechanical failure. for this reason only, low ? speed limits are programmed into the limit registers for the fans. it should be noted that, since fan period rather than speed is being measured, a fan failure interrupt will occur when the measurement exceeds the limit value.
nct80 http://onsemi.com 11 table 9. register map register name type reset value address offset configurationregister rw 0x08 0x00 statusregister1 ro 0x00 0x01 statusregister2 ro 0x00 0x02 maskregister1 rw 0x00 0x03 maskregister2 rw 0x00 0x04 fan_divisor_output_pin_config rw 0x14 0x05 os_config_temp_resolution rw 0x01 0x06 conversion_rate rw 0x00 0x07 channel_select_register rw 0x00 0x08 conversion_rate rw 0x00 0x09 in0_reading ro 0x0000 0x20 in1_reading ro 0x0000 0x21 in2_reading ro 0x0000 0x22 in3_reading ro 0x0000 0x23 in4_reading ro 0x0000 0x24 in5_reading ro 0x0000 0x25 in6_reading ro 0x0000 0x26 temp_reading ro 0x0000 0x27 tach1_reading ro 0x00 0x28 tach2_reading ro 0x00 0x29 in0_high_limit rw 0x00 0x2a in0_low_limit rw 0x00 0x2b in1_high_limit rw 0x00 0x2c in1_low_limit rw 0x00 0x2d in2_high_limit rw 0x00 0x2e in2_low_limit rw 0x00 0x2f in3_high_limit rw 0x00 0x30 in3_low_limit rw 0x00 0x31 in4_high_limit rw 0x00 0x32 in4_low_limit rw 0x00 0x33 in5_high_limit rw 0x00 0x34 in5_low_limit rw 0x00 0x35 in6_high_limit rw 0x00 0x36 in6_low_limit rw 0x00 0x37 hot_temp_high_limit rw 0x00 0x38 hot_temp_hysteresis_limit rw 0x00 0x39 os_temp_high_limit rw 0x00 0x3a os_temp_hysteresis_limit rw 0x00 0x3b tach1_count_limit rw 0x00 0x3c tach2_count_limit rw 0x00 0x3d manufacturerid ro 0x1a 0x3e
nct80 http://onsemi.com 12 configurationregister register information description allows the user to configure many features of the nct80 device. offset 0x00 bitfield details field name description access default 7 initialization setting this bit to 1 resets the main user writeable registers to their power on default values. rw 0 6 gpo setting this bit to 1 drives the gpo pin low. rw 0 5 chassis_clear setting this bit to 1 clears the gpi (chassis intrusion pin). after 10 ms this bit self clears. rw 0 4 reset setting this bit to 1 outputs at least a 10 ms reset (active low) pulse on rst_out . if bits 7 and 6 of register 0x05 are set to 1 and 0 respectively then this reset bit is cleared once the pulse is inactive. rw 0 3 int_clear setting this bit to 1 disables the int output. this does not affect the interrupt status registers/ the device will stop monitoring temperature and voltage. monitoring will resume upon the clearing of this bit. rw 1 2 int_polarity_select setting this bit to 1 selects an active high output while setting it to 0 selects active low output. rw 0 1 int_en setting this bit to 1 enables the int output. rw 0 0 start setting this bit to 1 enables the monitoring of temperature, voltage and fan readings. setting this bit to 0 disables these monitoring operations and effectively puts the device in shutdown mode. rw 0 statusregister1 register information description register to indicate if a high or low limit has been exceeded. offset 0x01 bitfield details field name description access default 7 int_in the nct80 sets this bit to 1 if a low has been detected on the int_in pin. ro 0 6 in6 the nct80 sets this bit to 1 if the high or low limit has been exceeded. ro 0 5 in5 the nct80 sets this bit to 1 if the high or low limit has been exceeded. ro 0 4 in4 the nct80 sets this bit to 1 if the high or low limit has been exceeded. ro 0 3 in3 the nct80 sets this bit to 1 if the high or low limit has been exceeded. ro 0 2 in2 the nct80 sets this bit to 1 if the high or low limit has been exceeded. ro 0 1 in1 the nct80 sets this bit to 1 if the high or low limit has been exceeded. ro 0 0 in0 the nct80 sets this bit to 1 if the high or low limit has been exceeded. ro 0
nct80 http://onsemi.com 13 statusregister2 register information description register to indicate if a high or low limit has been exceeded. offset 0x02 bitfield details field name description access default 7:6 reserved ro 0x0 5 os_bit the nct80 sets this bit to 1 if the temperature exceeds either the high or low os limit. the interrupt mode can be selected in register 0x04 bit 7. ro 0 4 gpi the nct80 sets this bit to 1 if the gpi (chassis intrusion) pin has gone high. ro 0 3 tach2 the nct80 sets this bit to 1 if the fan speed limit has been exceeded. ro 0 2 tach1 the nct80 sets this bit to 1 if the fan speed limit has been exceeded. ro 0 1 bti if this bit is set to 1 then it indicates that an interrupt has occurred on the board temperature input (bti ) pin. ro 0 0 temperature the nct80 sets this bit to 1 if the temperature exceeds either the high or low limit. the interrupt mode can be selected in register 0x04 bit 6. ro 0 maskregister1 register information description register to mask out of limit conditions shown in the corresponding status register. offset 0x03 bitfield details field name description access default 7 int_in writing a 1 to this bit disables the corresponding status bit for the int output. rw 0 6 in6 writing a 1 to this bit disables the corresponding status bit for the int output. rw 0 5 in5 writing a 1 to this bit disables the corresponding status bit for the int output. rw 0 4 in4 writing a 1 to this bit disables the corresponding status bit for the int output. rw 0 3 in3 writing a 1 to this bit disables the corresponding status bit for the int output. rw 0 2 in2 writing a 1 to this bit disables the corresponding status bit for the int output. rw 0 1 in1 writing a 1 to this bit disables the corresponding status bit for the int output. rw 0 0 in0 writing a 1 to this bit disables the corresponding status bit for the int output. rw 0
nct80 http://onsemi.com 14 maskregister2 register information description register to mask out of limit conditions shown in the corresponding status register. offset 0x04 bitfield details field name description access default 7 mode_select_os_ temp_interrupt writing zero to this bit selects the default interrupt mode which gives the user an interrupt if the temperature goes above the os limit. the interrupt will be cleared once the status register is read, but it will again be generated when the next conversion has completed. it will continue to do so until the temperature goes below the hysteresis limit. writing a 1 to this bit selects the one time interrupt mode which only gives the user one interrupt when it goes above the os limit. the interrupt will be cleared once the status register is read. another interrupt will not be generated until the temperature goes below the hysteresis limit. it will also be cleared if the status register is read. no more interrupts will be generated until the temperature goes above the os limit again. the corresponding bit will be cleared in the status register every time it is read but may not set again when the next conversion is done. rw 0 6 mode_select_hot_ temp_interrupt writing zero to this bit selects the default interrupt mode which gives the user an interrupt if the temperature goes above the hot limit. the interrupt will be cleared once the status register is read, but it will again be generated when the next conversion has completed. it will continue to do so until the temperature goes below the hysteresis limit. writing a 1 to this bit selects the one time interrupt mode which only gives the user one interrupt when it goes above the hot limit. the interrupt will be cleared once the status register is read. another interrupt will not be generated until the temperature goes below the hysteresis limit. it will also be cleared if the status register is read. no more interrupts will be generated until the temperature goes above the hot limit again. the corresponding bit will be cleared in the status register every time it is read but may not set again when the next conversion is done. rw 0 5 os_bit writing a 1 to this bit disables the corresponding status bit for the int output. rw 0 4 gpi writing a 1 to this bit disables the corresponding status bit for the int output. rw 0 3 tach2 writing a 1 to this bit disables the corresponding status bit for the int output. rw 0 2 tach1 writing a 1 to this bit disables the corresponding status bit for the int output. rw 0 1 bti writing a 1 to this bit disables the corresponding status bit for the int output. rw 0 0 temperature writing a 1 to this bit disables the corresponding status bit for the int output. rw 0
nct80 http://onsemi.com 15 fan_divisor_output_pin_config register information description this register allows the user to configure the tach reading modes and also the os and rst_out pin configuration. offset 0x05 bitfield details field name description access default 7 rst_en setting this bit to 1 enables the rst_out functionality on the rst_out / os output pin. if bits 6 and 7 are set to 0 then this pin is disabled. rw 0 6 os_pin_en setting this bit to 1 enables the os functionality on the rst_out / os output pin. for the os pin to function, bit 7 of this register must be set to 0. if bits 6 and 7 are set to 0 then this pin is disabled. rw 0 5:4 tach2_divisor if level sensitive input is selected setting bit <4> = 1 selects and active ? low input (an interrupt will be generated if the tach2 input is low), if bit <4> = 0 selects an active ? high input (an interrupt will be generated if the tach2 input is high). rw 0x1 0x0: divide by 1 0x1: divide by 2 0x2: divide by 4 0x3: divide by 8 3:2 tach1_divisor if level sensitive input is selected setting bit <2> = 1 selects and active ? low input (an interrupt will be generated if the tach1 input is low), if bit <2> = 0 selects an active ? high input (an interrupt will be generated if the tach1 input is high). rw 0x1 0x0: divide by 1 0x1: divide by 2 0x2: divide by 4 0x3: divide by 8 1 tach2_mode setting this bit to 1 selects the level sensitive input mode. setting this bit to 0 selects tach count mode for the input pin. rw 0 0 tach1_mode setting this bit to 1 selects the level sensitive input mode. setting this bit to 0 selects tach count mode for the input pin. rw 0
nct80 http://onsemi.com 16 os_config_temp_resolution register information description this register allows the user to configure the os output pin and also the temperature sensor resolution. offset 0x06 bitfield details field name description access default 7:4 temp_resolution depending of the state of bit 3 in this register these bits are the lsbs of the temperature measurement. if 8 bit resolution is selected then bit 7 only is the lsb of the temperature reading. if 11 bit resolution is selected then bits 7 ? 4 are the lsbs of the temperature data (bit 7 being the most significant of the 4 bits). rw 0x0 3 temp_resolution_ control selects either an 8 bit or 11 bit temperature conversion. rw 0 0: selects an 8 bit plus sign temperature conversion. 1: selects an 11 bit plus sign temperature conversion. 2 os_mode_select selects the mode of operation for the os pin. rw 0 0: 1: 1 os_polarity selects the polarity of the open drain os pin. rw 0 0: selects os to be active low. 1: selects os to be active high. 0 os_status this read only bit mirrors the state of the rst_out /os pin when the os pin is enabled. ro 1 conversion_rate register information description register to control the conversion rate of the adc input channels. offset 0x07 bitfield details field name description access default 7:1 reserved ro 0x00 0 conv_rate rw 0 0: sets the conversion rate to be ever 728 ms (typical). 1: sets the nct80 to operate in continuous conversion mode.
nct80 http://onsemi.com 17 channel_select_register register information description allows the user to manually add/remove measurement channels from the adc round robin loop. offset 0x08 bitfield details field name description access default 7 temp rw 0 0: this channel is included in the conversion loop. 1: this channel is disabled and conversions are skipped. value register will return 0 and it will not cause an interrupt to be generated. 6 in6 rw 0 0: this channel is included in the conversion loop. 1: this channel is disabled and conversions are skipped. value register will return 0 and it will not cause an interrupt to be generated. 5 in5 rw 0 0: this channel is included in the conversion loop. 1: this channel is disabled and conversions are skipped. value register will return 0 and it will not cause an interrupt to be generated. 4 in4 rw 0 0: this channel is included in the conversion loop. 1: this channel is disabled and conversions are skipped. value register will return 0 and it will not cause an interrupt to be generated. 3 in3 rw 0 0: this channel is included in the conversion loop. 1: this channel is disabled and conversions are skipped. value register will return 0 and it will not cause an interrupt to be generated. 2 in2 rw 0 0: this channel is included in the conversion loop. 1: this channel is disabled and conversions are skipped. value register will return 0 and it will not cause an interrupt to be generated. 1 in1 rw 0 0: this channel is included in the conversion loop. 1: this channel is disabled and conversions are skipped. value register will return 0 and it will not cause an interrupt to be generated. 0 in0 rw 0 0: this channel is included in the conversion loop. 1: this channel is disabled and conversions are skipped. value register will return 0 and it will not cause an interrupt to be generated.
nct80 http://onsemi.com 18 conversion_rate_programming register information description register to add further programmability to the conversion rate of the adc input channels. note any non ? zero value in this register over ? rides setting as controlled from register 07h offset 0x09 bitfield details field name description access default 7:3 reserved ro 0x00 2:0 conv_rate 0x00 use conversion rate as setup from register 0x07 bit 0 rw 0x0 0x01 conversion rate = 1.2 ms 0x02 conversion rate = 4.8 ms 0x03 conversion rate = 9.6 ms 0x04 conversion rate = 38 ms 0x05 conversion rate = 77 ms 0x06 conversion rate = 154 ms 0x07 conversion rate = 614 ms in0_reading register information description this register stores the data returned on this input channel offset 0x20 bitfield details field name description access default 15:6 in0_data ro 0x0000 in1_reading register information description this register stores the data returned on this input channel offset 0x21 bitfield details field name description access default 15:6 in1_data ro 0x0000 in2_reading register information description this register stores the data returned on this input channel offset 0x22 bitfield details field name description access default 15:6 in2_data ro 0x0000
nct80 http://onsemi.com 19 in3_reading register information description this register stores the data returned on this input channel offset 0x23 bitfield details field name description access default 15:6 in3_data ro 0x0000 in4_reading register information description this register stores the data returned on this input channel offset 0x24 bitfield details field name description access default 15:6 in4_data ro 0x0000 in5_reading register information description this register stores the data returned on this input channel offset 0x25 bitfield details field name description access default 15:6 in5_data ro 0x0000 in6_reading register information description this register stores the data returned on this input channel offset 0x26 bitfield details field name description access default 15:6 in6_data ro 0x0000 temp_reading register information description this register stores the data returned on the temperature channel offset 0x27 bitfield details field name description access default 15:4 temp_data ro 0x0000
nct80 http://onsemi.com 20 tach1_reading register information description this register stores the number of counts on the tach1 input pin. offset 0x28 bitfield details field name description access default 7:0 tach1_data ro 0x00 tach2_reading register information description this register stores the number of counts on the tach2 input pin. offset 0x29 bitfield details field name description access default 7:0 tach2_data ro 0x00 in0_high_limit register information description high limit register. offset 0x2a bitfield details field name description access default 7:0 high_limit rw 0x00 in0_low_limit register information description low limit register. offset 0x2b bitfield details field name description access default 7:0 low_limit rw 0x00 in1_high_limit register information description high limit register. offset 0x2c bitfield details field name description access default 7:0 high_limit rw 0x00
nct80 http://onsemi.com 21 in1_ low _limit register information description low limit register. low limit register. offset 0x2d 0x2d bitfield details field name description access default 7:0 low_limit rw 0x00 in2_high_limit register information description high limit register. offset 0x2e bitfield details field name description access default 7:0 high_limit rw 0x00 in2_low_limit register information description low limit register. offset 0x2f bitfield details field name description access default 7:0 low_limit rw 0x00 in3_high_limit register information description high limit register. offset 0x30 bitfield details field name description access default 7:0 high_limit rw 0x00 in3_low_limit register information description low limit register. offset 0x31 bitfield details field name description access default 7:0 low_limit rw 0x00
nct80 http://onsemi.com 22 in4_high_limit register information description high limit register. offset 0x32 bitfield details field name description access default 7:0 high_limit rw 0x00 in4_low_limit register information description low limit register. offset 0x33 bitfield details field name description access default 7:0 low_limit rw 0x00 in5_high_limit register information description high limit register. offset 0x34 bitfield details field name description access default 7:0 high_limit rw 0x00 in5_low_limit register information description low limit register. offset 0x35 bitfield details field name description access default 7:0 low_limit rw 0x00 in6_high_limit register information description high limit register. offset 0x36 bitfield details field name description access default 7:0 high_limit rw 0x00
nct80 http://onsemi.com 23 in6_low_limit register information description low limit register. offset 0x37 bitfield details field name description access default 7:0 low_limit rw 0x00 hot_temp_high_limit register information description hot temperature limit offset 0x38 bitfield details field name description access default 7:0 hot_temp_high_limit rw 0x55 hot_temp_hysteresis_limit register information description hysteresis temperature limit (low) offset 0x39 bitfield details field name description access default 7:0 hot_temp_hysteresis_limit rw 0x4b os_temp_high_limit register information description hot temperature limit offset 0x3a bitfield details field name description access default 7:0 hot_temp_high_limit rw 0x55 os_temp_hysteresis_limit register information description hysteresis temperature limit (low) offset 0x3b bitfield details field name description access default 7:0 hot_temp_hysteresis_limit rw 0x4b
nct80 http://onsemi.com 24 tach1_count_limit register information description tach1 speed limit. offset 0x3c bitfield details field name description access default 7:0 tach1_count_limit rw 0xff tach2_count_limit register information description tach2 speed limit. offset 0x3d bitfield details field name description access default 7:0 tach2_count_limit rw 0xff manufacturerid register information description manufacturer id register. 0x1a for on semiconductor. offset 0x3e bitfield details field name description access default 7:0 manufacturer id ro 0x1a
nct80 http://onsemi.com 25 serial bus interface control of the nct80 is carried out via the i 2 c bus. the nct80 is connected to this bus as a slave device, under the control of a master device. the nct80 has a 7 ? bit serial bus address. the upper 4 bits of the device address are 0101. the lower 3 bits are set by pins 22, 23 and 24. table 10 shows the 7 ? bit address for each of the pin states. the address pins are sampled continuously , so any changes made while power is on will result in the device address changing. table 10. i 2 c address options a2 a1 a0 address 0 0 0 0x28 0 0 1 0x29 0 1 0 0x2a 0 1 1 0x2b 1 0 0 0x2c 1 0 1 0x2d 1 1 0 0x2e 1 1 1 0x2f the serial bus protocol operates as follows: 1. the master initiates data transfer by establishing a start condition, defined as a high ? to ? low transition on the serial data line sda while the serial clock line, scl, remains high. this indicates that an address/data stream will follow. all slave peripherals connected to the serial bus respond to the start condition, and shift in the next eight bits, consisting of a 7 ? bit address (msb first) plus an r/w bit, which determines the direction of the data transfer, i.e., whether data will be written to or read from the slave device. the peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit. all other devices on the bus now remain idle while the selected device waits for data to be read from or written to it. if the r/w bit is a 0, the master will write to the slave device. if the r/w bit is a 1, the master will read from the slave device. 2. data is sent over the serial bus in sequences of nine clock pulses, eight bits of data followed by an acknowledge bit from the slave device. transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low ? to ? high transition when the clock is high may be interpreted as a stop signal. the number of data bytes that can be transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. 3. when all data bytes have been read or written, stop conditions are established. in write mode, the master will pull the data line high during the 10th clock pulse to assert a stop condition. in read mode, the master device will override the acknowledge bit by pulling the data line high during the low period before the ninth clock pulse. this is known as no acknowledge. the master will then take the data line low during the low period before the tenth clock pulse, then high during the tenth clock pulse to assert a stop condition. any number of bytes of data may be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation. in the case of the nct80, write operations contain either one or two bytes, and read operations contain one byte and perform the following functions. to write data to one of the device data registers or read data from it, the address pointer register must be set so that the correct data register is addressed, and then data can be written into that register or read from it. the first byte of a write operation always contains an address that is stored in the address pointer register. if data is to be written to the device, the write operation contains a second data byte that is written to the register selected by the address pointer register. this is illustrated in figure 20. the device address is sent over the bus followed by r/w set to 0. this is followed by two data bytes. the first data byte is the address of the internal data register to be written to, which is stored in the address pointer register. the second data byte is the data to be written to the internal data register. when reading data from a register there are two possibilities: 1. if the nct80?s address pointer register value is unknown or not the desired value, it is first necessary to set it to the correct value before data can be read from the desired data register. this is done by performing a write to the nct80 as before, but only the data byte containing the register address is sent, as data is not to be written to the register. this is shown in figure 16. a read operation is then performed consisting of the serial bus address, r/w bit set to 1, followed by the data byte read from the data register. this is shown in figure 18. 2. if the address pointer register is known to be already at the desired address, data can be read from the corresponding data register without first writing to the address pointer register, so figure 16 can be omitted. to read from a register it is necessary to first write the register address to the address pointer. the byte write protocol is used for this.
nct80 http://onsemi.com 26 slave address a sap register address 23 156 4 figure 15. byte write protocol w 0 scl sda 10 1 1 1 0 d7 d6 d5 d4 d3 d2 d1 d0 ack. by nct80 stop by master start by master frame 1 serial bus address byte frame 2 address pointer register byte 1 1 9 ack. by nct80 9 figure 16. writing to the address pointer r/w slave address data a r sp 24 3 156 figure 17. read byte protocol a 0 scl sda 10 1 1 1 0 d7 d6 d5 d4 d3 d2 d1 d0 no ack. by master stop by master start by master frame 1 serial bus address byte frame 2 data byte from nct80 1 1 9 ack. by nct80 9 figure 18. reading a byte from the nct80 r/w to write a byte to a particular register the following 3 ? byte sequence is used. the first byte is the 7 ? bit device address plus the write bit. the second byte is the register address to be written to and the third byte is the data to be written. slave address adata saap register address 23 15678 4 figure 19. write a byte to a register w 0 scl sda 10 1 1 1 0 d7 d6 d5 d4 d3 d2 d1 d0 ack. by nct80 start by master 19 1 ack. by nct80 9 d7 d6 d5 d4 d3 d2 d1 d0 ack. by nct80 stop by master 1 9 scl (continued) sda (continued) frame 1 serial bus address byte frame 2 address pointer register byte frame 3 data byte figure 20. writing a byte to a specified address r/w
nct80 http://onsemi.com 27 package dimensions tssop24 7.8x4.4, 0.65p case 948h issue b dim d min max 7.90 millimeters e1 4.30 4.50 a 1.20 a1 0.05 0.15 l 0.50 0.75 e 0.65 bsc c 0.09 0.20 b 0.19 0.30 l2 0.25 bsc m 0 8 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b does not include dambar protrusion. dambar protrusion shall be 0.08 max at mmc. dambar cannot be located on the lower radius of the foot. 4. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 per side. dimension d is determined at datum plane h. 5. dimension e1 does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 per side. dimension e1 is determined at datum plane h. 6. datums a and b are determined at datum plane h. 7. a1 is defined as the vertical distance from the seat- ing plane to the lowest point on the package body. 7.70 --- 24x 1.15 24x 0.42 0.65 dimensions: millimeters pitch soldering footprint e 6.40 bsc 6.70 recommended l l2 gauge detail a plane c detail a m end view c h 0.10 seating plane side view a c 0.05 c c 24x a1 pin 1 reference d e1 24x b e b m 0.10 a c top view b 0.15 c 112 13 24 a b note 3 2x 12 tips e note 6 note 6 note 4 note 5 s s s on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 nct80/d on semiconductor is licensed by philips corporation to carry the i 2 c bus protocol. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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